Fixed and floating point usage for Altera DE2?

Question

I'm suppsed to implement two versions of the an algorithm that does a finite impulse response in software, one algorithm with floating-point format and the other algorithm with fixed-point format. Now I think that if I just use float variables for the function then the algorithm will be done with floating-point:

The algorithm should work according to the spec

Before a new sample x*k* arrives the old samples are shifted to the right and then each sample is scaled with a coefficient before the result y*k*, the total sum of all scaled samples, is calculated

float[] FIRfloats = {0,0,0,0,0};
void floatFIR(float newsample)
{
for(int i=0;i<5;i++)
{
  FIRfloats[i+1]=FIRfloats[i]; /* shift the samples right */
}
FIRfloats[0]=newsample*0:0299;
FIRfloats[1]=FIRfloats[2]*0.4701;
FIRfloats[2]=FIRfloats[3]*0.4701;
FIRfloats[3]=FIRfloats[4]*0.0299;
}

And then I just sum the samples to get the floating-point format? Would this then be a software implementation of the FIR filter? And how can I do the fixed-point version?

Answer 1

No, you are not saving the samples in FIRfloats, you are saving the samples multiplied by a coefficient. Just save the samples in your array. Compute the products with the coefficients and save them in temporary variables, then sum the products to get the filter output value.

Converting this to fixed-point, and doing it well, is beyond the scope of what can be included here. Basically, you need to multiply all of your coefficients by some scale factor, say 2^16 (65536), and round to the nearest integer. Incoming samples should also be multiplied by a scale factor and cast to integers. Perform integer multiplication of the samples and coefficients, then an integer addition of the products. The result will have a scale factor that is the product of the scale factors of the coefficients and the input samples. Without knowing what you are going to do with the filter output it's hard to say what happens after that.

But you mention an Altera DE2 in your question. If this is intended for implementation in an FPGA shouldn't you be using Verilog or VHDL?