How do we declare multi-bit registers in verilog?

Question

In the declaration of a register, the sample code shows this:

reg[15:0]  regfile[0:15];

I don't understand why the [0:15] is inverted after the variable name. reg[15:0] declares a 16 bit register but why is it the other way around with the variable name?

Answer 1

Considering the terminology used by SystemVerilog, the [15:0] after the data type reg represents the packed array dimension. reg [15:0] is a 16-bit packed or integral type. An integral type can be used in an arithmetic expression. The 15 is the most significant bit(MSB) and the 0 is the least significant bit (LSB). Most computer systems have 0 as their LSB when indexing integral values.

The [0:15] that appears to the right of the declared variable name is the unpacked dimension. reg [15:0] regfile[0:15] is declaring an unpacked array of a packed array. In Verilog, you can only select one element of an unpacked array at a time to read or write to. So the only significance of numerical ordering of the unpacked dimension is when you call a routine like $readmemh. The first index on the left represents the first element to be loaded by default, and you usually want that to be 0. In SystemVerilog you can perform operations on an unpacked array as a whole aggregate, so the index ordering becomes more significant.

Verilog-2001 allows you declare multiple unpacked dimensions, but still you may only select one array element at a time. SystemVerilog allows multiple packed dimensions as well, plus the ability to perform certain operations like assignments and comparisons on the whole or portions of an unpacked array.

Answer 2

reg[15:0]  regfile[A:B];

is the shortcut for declaring (B-A+1) 16 bit registers which can be indexed using A,A+1..B

reg[15:0]  regfile[0:15];

declares

reg[15:0]  regfile[0];
reg[15:0]  regfile[1];
..................... 
reg[15:0]  regfile[14];
reg[15:0]  regfile[15];

It does the same if you invert the indices as below

reg[15:0]  regfile[15:0]; 

The following declares same but with different indices 10..24,25. Indices 0,1..9 are invalid.

reg[15:0]  regfile[25:10];

Answer 3

I believe it is more of a convention than a requirement. Refer to section 7.4.4 "Memories" in the IEEE Std 1800-2012, for example. Your regfile is considered a 16-bit wide memory with 16 locations.