Without more code I must add a little guessing, but could look like there is a
loop in the design in reslt
=> reslt_out1
=> reslt_out2
=> reslt
, since
there is no clock (clk
) on CL_Adder in the code:
reslt <= reslt_out2;
...
u8:CL_Adder port map(s_se, reslt, '0', reslt_out1, c1);
...
u9:CL_Adder port map(reslt_out1, s_se2, '1', reslt_out2, c2);
Whether this is the reason for the problem depends on how you see the
"undefined". In simulation the loop itself should not result in X
(unknown),
or similar, but the loop hints a problem. Btw, you mention "variables usage",
but there are no variables in the shown code; only signals.
Addition:
If the purpose is to accumulate the value, then a sequential process (clocked process to make flip flops) may be used to capture the result of each iteration, and present as argument in next iteration. The reslt <= reslt_out2;
may then be replaced with a process like:
process (clk, rst) is
begin
if rst = '1' then -- Reset if required
reslt <= (others => '0');
elsif rising_edge(clk) then -- Clock
reslt <= reslt_out2;
end if;
end process;