In top module, Q needed to be regs and D needed to be wires.
Quartus II - Verilog Flip Flop ModelSim Error
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25-09-2022 - |
Question
I am writing a simple flipflop module in verilog and I am trying to write a top level module in instantiate my flipflop module and simulate it in ModelSim.
Here is my code below,
module flipflop(clck,D,Q);
input clck,D;
output Q;
wire R,S,S_g,R_g,Qa,Qb;
assign R = ~D;
assign S = D;
nand(S_g,S,clck);
nand(R_g,R,clck);
nand(Qa,S_g,Qb);
nand(Qb,R_g,Qa);
assign Q = Qa;
endmodule
module TopLevel();
reg clck;
reg Q;
wire D;
flipflop p1(clck,D,Q);
always begin
#5 clck <=1;
#5 clck <=0;
end
endmodule
When I compile this code it runs fine, but when I try to simulate it, I get the following error:
# ** Error: (vsim-3053) C:/altera/13.1/FlipFlopsProjects/flipflop.v(30): Illegal output or inout port connection for "port 'Q'".
Any ideas or thoughts?
La solution 2
Autres conseils
Error was in the declaration of inputs for the top level module...they needed to be wires, not regs
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