What determines an architectures byte size?

Question

Am I correct in saying that if I construct a RAM of x storage locations, each of which is y-bits wide, then I have xybits of y-bit RAM?

Questions such as this one explain with historical examples why we cannot rely on 8b == 1B, but I cannot find confirmation of what this means in terms of architecture.

Answer 1

Slightly older, and slightly wiser, I think I can answer my own question.

Given an N-bit address bus, there are 2^N addressable memory locations.

If an M-bit data bus is desired, then log M bits address columns, and N - log M address rows into the RAM.

So back to the question; N := x, M := y, and we have y*2^x bits of y-bit RAM.

For numerical example, suppose a 12-bit address and 16-bit data. 8 bits address 2^8 = 256 rows; the remaining 4 bits address 16x 16:1 multiplexers on the columns, giving 16 bits of data output. (As shown above).