VHDL- vector slicing

Question

I have input std_logic_vector of (0 to X). Range of x is 0 to 1000 bytes and the code should support any value of X. I would like to slice the input into 128 bit blocks, for further processing and operations. a) how can it be done? b) is there a way to make the following pseudo-code work? so i can adopt it for solving a)? i need to use the loop index for naming the signals but i guess its not possible with VHDL (?)

for i in 0 to N loop

  block_i <= input (X, X-127);

end loop; 

Thanks in advance.

Answer 1

Something like this ?

library ieee;
use ieee.std_logic_1164.all;

entity slicer is
  generic(X : natural:=1000);
  port (input : in std_logic_vector(X*128-1 downto 0));
end entity;

architecture rtl of slicer is
  type block_type is array(0 to X-1) of std_logic_vector(127 downto 0);
  signal blocks : block_type;
begin

slicing:for i in 0 to X-1 generate
            blocks(i) <= input(128*(i+1)-1 downto 128*i);
        end generate;

end rtl;

Answer 2

You have a few options with how to accomplish this. One is to use the flattened 1-D array that is selectively sliced as demonstrated by @JCLL. Another option is to create a new type that is an array of an array.

subtype word is std_logic_vector(127 downto 0); -- Constrained subtype
type word_vec is array(natural range <>) of word; -- New unconstrained type
...

entity foo is
    port (
        X : in word_vec -- Get our constraint when instantiated
    );
end entity;

...

for i in X'range loop
    blocks(i) <= X(i);
end loop;

This solution skips the arithmetic needed for the 1-D slicing but is limited by the need for a constrained type for the elements of word_vec. This last limitation is lifted in VHDL-2008 where you can do the following:

-- Both unconstrained arrays
type word_vec is array(natural range <>) of std_logic_vector;

The best solution depends on what your task is and how much flexibility you need for size changes in the future.

A final less appealing option is to use a 2-D array but that gets ugly when you need more than bitwise access.

Answer 3

Yes, you can assign parts of a large logic vector to another smaller vector. I'm not sure about your specific implementation (you did not provide the signal types and sizes -- is the large vector 1000 bytes or 1000 bits?). However, If you know what X is at time of synthesis, use generics, like

entity foo is
    generic(X : Natural);
    port(input: in std_logic_vector(X-1 downto 0); 
         block_i: out std_logic_vector(127 downto 0));

end entity; 

Otherwise you just need to pass in a size as well:

entity foo is
    port(input: in std_logic_vector(X-1 downto 0);
         block_i: out std_logic_vector(127 downto 0);
         X    : in Natural);
    end entity;

And then use the size when you are assigning parts to block_i.

Note that you will need to either use the generic or a hard-coded constant (ie: 1000 for the worse case) for the loop. VHDL does not like variable loop ranges. You can work around this, but I usually don't need to (see: Using FOR loop in VHDL with a variable)