Correctly handling data abort exception when branch follows load

Question

I am somewhat confused with proper way to handle data abort exceptions on ARM CPU.

For example this document says that when data abort exception state is entered LR register is set to the address of PC-8. I assume that the 2 instructions following faulty load or store instruction got fetched into the pipeline. But is it really safe to return to the PC-8 address. What if the instruction immediately following faulty load instruction was a branch. Does it mean that PC register is actually set to the branch destination instruction and not the one that sequentially follows the load instruction. In this case returning to PC-8 will return to some random place in the program 2 steps behind the branch destination ) and not to the faulty load instruction. Am I missing something here?

Answer 1

If an LDR or STR aborts and one of the two following instructions is a branch then the branch will not have had any effect yet and the LR of Abort mode will contain the address of the aborting instruction + 8. So LR-8 is the address to return to if you want to re-execute the aborting instruction.