Transaction size and latency between: CPU and RAM, RAM and PCIE2.0 16x device

Question

What is the minimum transaction size in bytes, and what with the latency in clock cycles or nanoseconds?
For:

1. access the CPU(Sandy/Ivy Bridge) to RAM
2. DMA access between the RAM and the device by PCIE 2.0 16x

Answer 1

To answer the question (partly)

2: A few (chip to chip) figures are in the paper here (at the end, Table 1 and 2)

Note also that the latency depends also on how big the PCIE packets are.

To complicate it there is also some latency introduced by the OS and the Graphiccards driver (reading/writing memory, User-Kernel land switching time, and so on).

Answer 2

Minimum transfer size is 0 which does not have any effect at both sides. With data, minimum transfer size is 1 doubleword(4 bytes)