x86_64 memory reorder

Question

on x86_64 architecture, whether the following code will always hold:

A=1;B=1;

Thread1 : store A=2; store B=3; Thread2 : load B==3; load A==2

is there any posibilities that B==3 but A==1 ??

Answer 1

Chapter 8.2.3 of Volumes 3A and 3B of the Intel architecture manual go into great depth on this subject, however, for your case (8.2.3.7 Stores Are Seen in a Consistent Order by Other Processors), there is strict ordering, which means writes are observed in the order in which they are made, making it impossible for B to read the updated value while A still has the old value.

It should be noted that its generally a good idea to provide explicit barriers in cases like this by using the various memory fencing instructions available, SFENCE,LFENCE & MFENCE via _mm_sfence, _mm_lfence & _mm_mfence. under x64 you also have the option of __faststorefence(MSVC only).