sc_buffer
and sc_signal
are both primitive channels that implement sc_signal_inout_if
; a 'buffer' is an object of type sc_buffer
, while a 'signal' is an object of type sc_signal
. The only difference between the two is that you get a value-change event whenever a buffer is written, whether or not it changes value.
There's no equivalent in Verilog, so nothing to do with wires and registers. There is something similar in VHDL. <sig>'transaction
gives you an implicit signal which toggles between '0' and '1' in a delta cycle whenever <sig>
is written to, irrespective of whether or not <sig>
changes. <sig>'event
is only true in a delta when <sig>
has actually changed.
So, in short, use a buffer when you need to know if a channel has been written to, even if the write didn't change anything.