Are memory visibility problems per thread also there if there is just one CPU core?

Question

Title might seem weird, so let me explain. Often people teaching about race conditions say thread1 can see x == 0 while thread 2 already did x=1;

My questions is about threads scheduled on same core(not unrealistic, there are still 1 core embeded systems and afaik you could prob at least in theory bind threads to cores) :
Do usual race visibility problems can occur even if thread1 and thread2 run sequentially(one befor/after another( with other threads ofc)) on the same core(X86, ARM)...

Answer 1

It is still a problem. Threads running on a single core is not unrealistic at all. Typically, you would have hundreds of threads running, but most likely you don't have hundreds of cores. By pigeon hole theorem, at least two of those threads share a core.

The race condition arises because the threads in fact are not sequential. It is true that they take turn running, but they get interrupted and the CPU is transferred to the other thread unpredictably. Imagine these two (imaginary) assembly programs

       Thread 1                    Thread 2

A:  Read  R1, 0x0100        E:  Read  R2, 0x0100
B:  Inc   R1                F:  Dec   R2
C:  Store R1, 0x0100        G:  Store R2, 0x0100

If you run this code sequentially, there is no problem. However, if you are allowed to interrupt them, then something like this could happen:

• A is run
• B is run
• Thread 1 interrupted
• E is run
• F is run
• G is run
• Thread 2 finished
• C is run

If you track what happens to the registers and the value at address 0x0100, then you will realize that the end value is not the same as sequentially executing the two pieces of code.

So the answer to your question is that the race happens in preemptable threads on the same CPU core just as it would as if the threads were run on separate cores.