EDIT 1:
Your Code Edited with reset logic, notice the addition of the RESET
signal to the ports list, the deletion of the asynchronous line setting that value, addition of RESET
to the sensitivity list of your CounterProcess
process, the addition of the if(RESET = '1')
line, and change of your if
to an elsif
, as well as the change of your shifting line:
I actually don't know what your An <= Anode
line is doing, and believe this to be in error also.
entity Main is PORT(
RESET: in std_logic;
CLK: in std_logic;
LED: out std_logic_vector(7 downto 0);
Switch: in std_logic_vector(7 downto 0);
Segment: out std_logic_vector(7 downto 0);
AN: out std_logic_vector(3 downto 0)
);
end Main;
architecture Behavioral of Main is
signal counter: std_logic_vector(7 downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit: std_logic_vector(25 downto 0);
signal anode: std_logic_vector(3 downto 0);
begin
ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz;
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <= "00000000000000000000000001"; -- 50 MHz
end case;
end process;
CounterProcess: process(RESET, CLK, Switch)
begin
if(RESET = '1') then
AN <= "0001";
elsif rising_edge(CLK) then
if prescaler < limit then
prescaler <= prescaler + 1;
else
prescaler <= (others => '0');
counter <= counter + 1;
AN <= std_logic_vector(unsigned(AN) sll 1);
end if;
end if;
end process;
An <= anode;
Segment <= counter;
end Behavioral;
you need to write the line that you currently have:
AN sll 1;
as
AN <= AN sll 1;
Remember that AN
is essentially like a variable that needs to be "set". Like your line above
counter <= counter + 1;