MSP540F5438A Clock Bringup

Question

I'm new to the MSP430 and I am trying to better understand the clock bring-up process. For my current purpose I'm going to take PMMCOREV out of the equation by using a 4 MHz MCLK which is within the 0-8 MHz range for PMMCOREV = 0.

Will someone knowledgable about these parts please check my logic and assumptions:

When the part boots XT1 is selected as the FLL reference and DCOCLKDIV is selected as the MCLK input. DIVM is 0 so the MCLK source is not divided.

When the system boots the crystal is not yet stable so I'm assuming the UCS moves in to fail-safe mode and uses REFO (internal trimmed 32K) as the FLL reference.

Already I'm a bit confused. If the divided DCO is used for MCLK how are we assured that the FLL is stable? So how is the core functioning at all?

It seems to me that MCLK should be either VLO or REFO until you can bring things up gracefully.

Can someone clarify these details and steer me in the right direction to properly initialize these clocks?

Thanks!

Answer 1

Per your comment, yes.

At startup DCO will be the clock - so you just need to modify the UCSCTL registers and wait for the oscillators to settle and you are good to go.

Here are the steps in general:

1. Change the vcore level in steps (if necessary - in your case its not)
2. Enable XT1
3. Configure the drive strength
4. Select your clock sources for MCLK, SMCLK, and ACLK and do any source division that you need to do
5. Allow XT1, XT2 and DCO to stablize by checking for fault flags.

Your external crystal is 4Mhz - Are you wanting to use it as MCLK directly? Or is your angle to use it as a reference to the FLL for DCO, and use DCO for MCLK (to achieve a higher MCLK frequency)? The core volatage that you will need depends on whatever your MCLK frequency is, not your external crystal's frequency. So if you are wanting to use a MCLK rate of higher than 8Mhz you will need to consider stepping up PMMCOREV to 01.

For convenience, here is a reference for UCS registers from SLAU208M. http://www.ti.com/lit/ug/slau208m/slau208m.pdf#page=172

Based on your OP, I think you should do the following if you want to use XT1 are your MCLK:

//1) Enable XT1 - XT1 will be off by default. You may not need to explicitly
//   perform this step. According to pg. 162 in SLAU208M, XT1 will be
//   enabled when you select it as the source for one of the clocks. But I
//   like being explicit!
UCSCTL6 &= ~XT1OFF //XT1OFF= 0x0001u

//2) Clear the XT1DRIVE bits - it may not be necessary to clear these bits
//   explicitly, but XT1's drive strength can be reduced to 0 w/ a 4MHz
//   crystal. By default, this will be b11, full scale, which will consume
//   more power, but result in a quicker settling time.
UCSCTL6 &= ~XT1DRIVE0; //XT1DRIVE0 = 0x0040u
UCSCTL6 &= ~XT1DRIVE1; //XT1DRIVE1 = 0x0080u

//3) Select XT1 as the clock source for XT1. UCSCTL4 defaults to 0x44 at
//   power on - DCOCLKDIV (b100). SELM_XT1CLK = b000.
UCSCTL4 &= SELM__XT1CLK; //SELM__XT1CLK = 0x0000u

//4) Wait for XT1 to stabilize
do
{
   //Explicitly clear the XT1 low and high frequency fault flasg, XT2 fault flag,
   //and DCO fault flag. 0X0008u, 0x0002, 0x0004, 0x0001 respectively.
   UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); 
   //Clear the oscillator fault interrupt flag in the special function interrupt
   //flags register.
   SFRIFG1 &= ~OFIFG; //0X0002U
} while (SFRIFG1&OFIFG); //Test to see if any oscillator fault flags are asserted.

I am using IAR systems, not sure if you are using CCS if those definitions will be named differently. I went ahead and typed out the hex for each of the operands.

On the msp4305438A you do not have to do anything with bypass.

Does that answer your question?

Also, in your OP you mention wanting to use XT1 as a reference for an FLL. That is accomplished using UCSCTL3. SELFREF is the field you want to set to b000 to use XT1,

Here's the definitions for the MSP4305438A header in IAR:

#define SELREF0             (0x0010u)    /* FLL Reference Clock Select Bit : 0 */
#define SELREF1             (0x0020u)    /* FLL Reference Clock Select Bit : 1 */
#define SELREF2             (0x0040u)    /* FLL Reference Clock Select Bit : 2 */