Driving module output from combinatorial block

Question

1. Is it a good design practice to use combinatorial logic to drive the output of a module in VHDL/Verilog?

2. Is it okay to use the module input directly inside a combinatorial block,and use the output of that combinatorial block to drive another sequential block in the same module?

Answer 1

An answer to the two questions really depends on the overall design methodology and conditions, and will be opinion based, as Morgan points out in his comment.

The questions are in special relevant for a large design with timing pushed to the limit, and where multiple designers contribute with different modules. In this case it is important to determine a design methodology up front which answers the two questions, in order to ensure that modules provided by different designers can be integrated smoothly without timing issues.

Designing with flip-flops on all outputs of each module, gives the advantage that when an output is used as input to other module, then the input timing is reasonable well defined, and only depends on the routing delay. This makes it a Yes to question 1.

Having a reasonable well-defined input timing makes it possible to make complex combinatorial logic directly on the inputs, since most of the clock cycle will be available for this. So this also makes it a Yes to question 2.

With the above Yes/Yes design methodology, the available cycle time is only used once, and that is at the input side of the module, before the flip-flops that goes on the output. The result is that multiple modules will click nicely together like LEGO bricks, as shown in the figure below.

If a strict design methodology is not adhered to in different modules, then some modules may place flip-flops on the input, and some on the output. A longer cycle time, thus slower frequency, is then required, since the worst case path goes through twice the depth of combinatorial logic. Such a design is shown in the figure below, and should be avoided.

A third option exists, where flip-flops are placed on all inputs, and the design will look like the figure below if two different modules use the same output.

One disadvantage with this approach is that the number of flip-flops may be higher, since the same output is used as input to multiple flip-flops, and the synthesis tool may not combine these equivalent flip-flops. And even more flip-flops than this may be required, if the module that generates the output will also have to make a flip-flopped version for internal use, which is often the case.

So the short answer to the questions is: Yes and Yes.

Answer 2

The answer to both questions as expressed is basically yes, provided the final design meets speed targets, and the input signals are clean.

The problem with blocks designed this way are that the signal timings through them are not accurately defined, so that combining several such blocks may result in an absurdly slow design, or one in which fast input signals don't propagate cleanly through the design.

If you design such a circuit, and it meets ALL your input and output timing constraints as well as any clock speed constraints you set, it will work.

However if it fails to meet the clock constraints you will have to insert registers to "pipeline" the design, breaking up long slow chains of combinational logic. And you will have to observe the input and output timings reported by synthesis and PAR, and they can get complicated.

In practice (in an FPGA : ASICs can be different) registers are free with each logic block (Xilinx/Altera, not true for Actel/Microsemi) and placing registers on each block's inputs and/or outputs makes the timings much simpler to understand and analyse.

And because such a design is pipelined, it is normally also much faster.