Analyze a packed structure in SystemVerilog to determine it's size?

Question

In SystemVerilog is there a way to analyze a packed structure and determine it's overall size in bits?

typedef struct packed unsigned {
    logic [15:0]    field_1;
    logic  [7:0]    field_2;
    logic [15:0]    field_3;
    logic  [4:0]    field_4;
} my_struct;

For example, I would like to be able to determine programmatic-ally that the size of the above structure is 45.

I've looked at the "Aggregate data types" section (Chapter 7) of the IEEE 1800-2012 SystemVerilog Language Reference Manual, and didn't see anything like this.

Is this possible? If so, how?

Answer 1

Use $bits() from IEEE 1800-2012 § 20.6.2 Expression size system function:

The $bits system function returns the number of bits required to hold an expression as a bit stream.

Direct example from the LRM:

... Given the declaration:

typedef struct {
logic valid;
bit [8:1] data;
} MyType;

the expression $bits(MyType) shall return 9, the number of data bits needed by a variable of type MyType.