theta_a
and p1
are inferring latching logic. This is usually synthesizes to be big, complex, brittle logic. Making them flip-flops should remove your issue.
always@(posedge clk) begin
if(r == div) begin
//tick <= ~tick; // tick can be optimized out
theta_a <= (theta_a + 8'b1) % 8'd255; // theta_a is flopped
r <= 1;
end
else begin
r <= r + 1;
end
end
always@(posedge clk) begin
theta_tri <= (theta_tri + 8'b1) % 8'd255;
end
//generate spwm
always@(posedge clk) begin // latch to flip-flop
if ($signed(sine_a) > $signed(tri_out))
p1 <= 1'b1;
else if ($signed(sine_a) < $signed(tri_out))
p1 <= 1'b0;
end
FYI: you may also want to check if there are latches in your SINE_LUT
and TRI_LUT
. If your synthesizer has a decent optimization phase, then THETA_HLP
and THETA_TMP
will be combinatorial logic. A brute force synthesizer could create latches. To guaranty combinatorial logic, make sure THETA_HLP
and THETA_TMP
are always assigned a value.
Convert:
if (THETA[6:0] == 7'd64) begin
...
end
else begin
if (THETA[6]) begin
THETA_HLP = 7'd64 - {1'd0, THETA[5:0]};
THETA_TMP = {THETA_HLP[5:0]};
end
else begin
THETA_TMP = {THETA[5:0]};
end
case (THETA_TMP)
...
endcase
end
to:
THETA_HLP = 7'd64 - {1'd0, THETA[5:0]};
THETA_TMP = THETA[6] ? THETA_HLP[5:0] : THETA[6];
if (THETA[6:0] == 7'd64) begin
...
end
else begin
case (THETA_TMP)
...
endcase
end
THETA_HLP
and THETA_TMP
are continuously assigned combinatorial logic and functionally equivalent to your original.