Verilog: Reading 1 bit input and Writing it to 288 bit reg

Question

In verilog, I have a module name(input data,..., output...);
Data is only a single bit input and I need it to be displayed to reg [288:0] data_tmp; to compare the bits. How do I transfer data(input) to the reg?

I tried to handle it like an array in C using a for loop like so:

for(i=0; i<288; i=i+1) begin
    data_tmp[i]=data;
end

But it doesn't appear to take any of the values from data or it is overwriting them.

Actual Code:

module inspector (
input rst_n, data, clk,
output total_cnt, skype_cnt, ftp_cnt, https_cnt, telnet_cnt, ssh_cnt, snmp_cnt, smtp_cnt,
      nntp_cnt, telnet_session, skype_session, ssh_session
);

output [31:0] total_cnt;
output [7:0] skype_cnt;
output [7:0] ftp_cnt;
output [7:0] https_cnt;
output [7:0] telnet_cnt;
output [7:0] ssh_cnt;
output [7:0] snmp_cnt;
output [7:0] smtp_cnt;
output [7:0] nntp_cnt;
output [7:0] telnet_session;
output [7:0] skype_session;
output [7:0] ssh_session;

localparam INIT  = 0;
localparam DATA = 1;
localparam PORT = 2;
localparam TOTAL = 3;


reg [287:0] data_tmp;

reg [3:0] Start_sequence = 32'hA5A5A5A5;

reg [1:0] state;

integer i;

always @(posedge clk)

    if (rst_n) begin
        total_cnt_tmp = 8'h00;
        ....
        ssh_session_tmp = 8'h00;
    end else begin
        case (state)
            INIT    : begin
                for(i=0; i<288; i=i+1) begin
                    data_tmp[i]=data;
                end

                if (data_tmp[31:0] == Start_sequence) begin
                    state <= DATA;
                end else begin
                    state <= INIT;          
                end
            end
   .....

Answer 1

The for-loop is replicating the data; ie if data is 1 you get 288 ones, if data is 0 you get 288 zeros. What you want what is a shifter. data_tmp shift the bits to the left or right depending on the order of the bit stream.

data_tmp<={data_tmp[286:0],data}; // shift and fill left

or

data_tmp<={data,data_tmp[287:1]}; // shift and fill right

Also, remember to assign flops with non-blocking (<=). Blocking (=) for assigning combinational logic.