What is the difference between elseif and elsif in VHDL

Question

Currently, I've been involved in FPGA design techniques using Xilinix. While solving design problems, I repeatedly found the use of elseif and elsif in if-chain almost for similar statements.

elsif(clk'event and clk='1') then
                 pr_state<=nx_state;

and

elseif S1=’0’ and  S0=’1’ then
     Z <= B;

My problem is- what's the difference between these two constructs? Are they similar? I've gone through D.L. Perry's VHDL book and other online VHDL tutorials' sites but can't find solution.Thanks in advance!

Answer 1

As you can see here
http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html
elseif is not a valid keyword in vhdl. So if it is recognized, then some tool vendor wanted to do you a favour... I would guess that you actually saw else if, as pointed out above

Answer 2

It looks like the correct syntax is elsif. There's no mention of elseif in any VHDL reference. http://www.eda.org/rassp/vhdl/guidelines/vhdlqrc.pdf
http://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.html
http://www.lsi.die.upm.es/~angelfh/LCSE/docs/Synario_VHDL_Reference_Manual_1997.pdf