mixed VHDL & Verilog designs: which free simulation and/or synthesis tools?

Question

I'm developping a mixed-hdl design using VHDL and Verilog IP's.

Which tool can I use to simulate and synthetize it for free if my target FPGA vendor is not chosen yet?

Answer 1

Xilinx ISIM certainly can do mixed language simulations. Last time I used it much, there were limitations : I could only add Verilog memory models to the top level of my VHDL design, not in a sub-level (representing a SODIMM module) and there were some stupid port connection bugs, possibly now fixed.

Avoid using Xilinx IP and it'll simulate vendor neutral code, though technically that may violate the license agreement.

Post-synthesis netlists may be in either language, but if your memory models are only available in Verilog and your testbenches are VHDL, that doesn't help much...

Answer 2

I don't think there are any free simulators out there that do mixed language designs. Perhaps Xilinx isim can do mixed language this, but you are only allowed to simulate designs that are targeted at Xilinx (read the license agreement for more details).

More free simulators: http://www.sigasi.com/faq/which-free-vhdl-simulator-can-i-use

Free synthesis tools are provided by the FPGA vendors. That is: free of charge, for the smaller FPGA chips.

Answer 3

Icarus Verilog - http://iverilog.icarus.com/

There's a vvp_embedded branch of the code I created for analog mixed-signal (with Spice/Gnucap). I could probably try to integrate a VHDL simulator if someone is interested in helping.

Personally I think VHDL is an awful language that fails on many counts, so I usually avoid it.