The warning has been explicitly described in Xilinx WP309 Targeting and Retargeting Guide for Spartan-6 FPGAs [P9-11].
To reduce cost of the overall architecture, slices in Spartan-6 FPGAs do not have a REV
pin. As a result, flip-flops no longer implement both a set signal and a reset signal. In
addition, a register with a set or reset signal can only have an initialization value of
the same polarity. For example, a flip-flop with an asynchronous reset can only have an
initialization value of 0.
That is to say, the following kinds of registers/latches are NOT RECOMMENDED when using Xilinx Spartan-6 FPGAs:
______|______
| Set |
| |
---| D Q |--- -- 1. a register/latch with both ASYNCHRONOUS
| _ | set and reset signals
---|>Clk Q |o-- -- NOT RECOMMENDED
| |
| Reset |
|___________|
|
-- 2. a register/latch described with an ASYNCHRONOUS set/reset which
however has an initialization value of the opposite polarity
-- The default value of reg is 0 which is the left
-- bound value of the integer type definition.
signal reg: integer range 0 to 7; <-----
|
process (clk, reset) |___ opposite
begin | NOT RECOMMENDED
if (reset = '0') then |
reg <= 7; <-----
elsif ( rising_edge(clk) ) then
reg <= val;
end if;
end process;
Solutions recommended by Xilinx:
1. Remove either the set or reset from all registers and latches
if not needed for required functionality
2. Modify the code in order to produce a synchronous set and/or
reset (both is preferred)
3. Ensure all registers have the same initialization value as the
described asynchronous set or reset polarity
4. Use the -async_to_sync option to transform the asynchronous
set/reset to synchronous operation
(timing simulation highly recommended when using this option)
In your design, you can either initialize TmrCnt
to TmrInit
or count TmrCnt
in an upward direction.