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UART RS-232 Transmitter

https://www.generacodice.com/it/articolo/13641994/uart-rs-232-transmitter
  serial-port  -  vhdl  -  fpga
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Reading different data on a single line from file in VHDL

https://www.generacodice.com/it/articolo/13637908/reading-different-data-on-a-single-line-from-file-in-vhdl
  file  -  vhdl
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VHDL code not running properly on Nexys2

https://www.generacodice.com/it/articolo/13631206/vhdl-code-not-running-properly-on-nexys2
  vhdl  -  fpga
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VHDL testbench for Modelsim (Altera)

https://www.generacodice.com/it/articolo/13628680/vhdl-testbench-for-modelsim-altera
  vhdl  -  modelsim  -  hdl  -  intel-fpga
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Trouble having port mapping two modules in one

https://www.generacodice.com/it/articolo/13601446/trouble-having-port-mapping-two-modules-in-one
  vhdl
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VHDL simple optimization

https://www.generacodice.com/it/articolo/13598197/vhdl-simple-optimization
  vhdl
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VHDL: Zero-Extend a fixed signal value

https://www.generacodice.com/it/articolo/13586530/vhdl-zero-extend-a-fixed-signal-value
  vhdl
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Signal led cannot be synthesized, bad synchronous description?

https://www.generacodice.com/it/articolo/13570384/signal-led-cannot-be-synthesized-bad-synchronous-description
  vhdl  -  fpga  -  xilinx
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get dependencies of vhdl entity in modelsim

https://www.generacodice.com/it/articolo/13560316/get-dependencies-of-vhdl-entity-in-modelsim
  dependencies  -  tcl  -  vhdl  -  modelsim
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Clock divider simulation

https://www.generacodice.com/it/articolo/13551700/clock-divider-simulation
  vhdl
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