Simple Adder Control Signals on Zynq SoC - Zedboard

Question

I am new to the Zedboard and am working up to transferring a complex hardware accelerator I currently have working on a regular FPGA board. Anyway I want to walk before I can run so have done the Zedboard speedway tutorials and am now toying around with small projects. My first of which being an simple adder accelerator:

-Send 2 numbers to the pl(programmable logic), to reg a and b

-the pl adds the numbers

-an interrupt to the PS(CPU) signals the computation has finished.

-In the ISR the PS reads the result from reg c

For this design I am using 3 registers (a,b,c) in the AXI interconnect, I have created the IP templates using CIP.

Basically though what is the best way send a control signal to enable the addition to the PL. So how should I signal to the PL adder that I have loaded the two numbers in reg a and b and now want to add them?

-Should I create a 1bit signal GPIO interconnect, add a 4th 1 bit control register to the IP? or is there a more 'stylish' way to do this by using the BUS2IPdata signals?

-Or is there another way to create custom PS to PL control enable signals?

Many thanks Sam

Current idea:

-Build a switch in the user_logic HDL based on the BUS2IPWrCE, so when this is asserted to write to reg B I can then signal an enable signal to my adder? Or will I run into some concurrency issues with the data not being fully written straight away?

Answer 1

So to do this I have created the AXI perph using CIP, then modified the used_logic and two new ports, en and interrupt. Following these instructions I employed these external connections.http://www.programmableplanet.com/author.asp?section_id=2142&doc_id=264841

I then connected these two external connections to GPIO interfaces to provide the required functionality.

Answer 2

In your larger designs, it will be difficult to get performance using a GPIOs to control the scheduling of your accelerators. I suggest setting up FIFOs of command blocks between software and hardware.

For example, your peripheral could implement an AXI Stream slave, to receive commands from software, and an AXI Stream master, to send result indications back to software.

It can assert an interrupt to indicate that there are values in the response FIFO.

For higher performance, set up these FIFOs in DRAM and use AXI read/write masters in your peripheral.