Read first synchronous RAM in Altera Quartus for Cyclone II

Question

is there a simple way to make inferred synchronous RAM with read-first then write logic for Altera Cyclone II?

I need this to implement cancel option into my RAM’s driver.

I am thinking about some state machine that first reads the memory and remembers it in DFF and after that writes to it, but honestly, I have no idea how to even start writing it. And maybe there’s simpler solution?

Answer 1

Something like this should result into the desired behavior (read old value and write new value):

process (clk)
begin
  if (clk'event and clk = '1') then
      if (write_enable = '1') then
          ram_block(write_address) <= new_data;
      end if;
      old_data <= ram_block(read_address);
  end if;
end process;