Is L2 inclusive Or non-inclusive in i7 CPU 860 @ 2.80GHz? [closed]

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I am interested to find the inclusive/exclusive nature of L2 cache in Intel i7 series (i7 CPU 860 @ 2.80GHz).

Here I find two links related to CPU details of i7 CPU 860 @ 2.80GHz and both are contradictory. I am confused and unable to finalize the nature of L2 cache about inclusive/exclusive nature.

bit-tech says L2 is inclusive whereas cpu-world says L2 is non-inclusive. It will be great if anyone give some insight or links to help me to figure out the nature of inclusive/exclusive of L2 cache.

Is there any ways to figure out the inclusive/exclusive nature of L2 cache ( programmatically or other way) ?

Answer 1

This answer applies here as well.
According to the optimization guide, in section 2.4.4 dealing with Nehalem generation caches:

The L1 and L2 caches are writeback and non-inclusive.
The shared L3 cache is writeback and inclusive

This must be a typo in the 2nd article, note that in the text itself the inclusiveness is only mentioned regarding the L3, they must have copy pasted it in the summary below.

There is also not much sense in making 2 levels inclusive, the L3 already serves to filter snoops.