higher frequency clock generation in RTL

Question

I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.

Answer 1

A pure Verilog solution is not stable, so dedicated FPGA resources must be used.

Please see this previous answer; it applies to Verilog also, even through tagged VHDL.