For synthesis, you need to represent the real number in a binary format (fixed-point or floating point, depending on what range you want). VHDL-2008 provides a few packages with conversion functions to make this easier. For instance, if you're using floating point:
use ieee.float_pkg.all;
...
signal float_real : real;
signal float_bin32 : float32;
signal float_slv : std_logic_vector(31 downto 0);
signal float_sum : float32;
...
float_bin32 <= to_float(float_real);
float_sum <= float_bin32 + 0.002;
float_slv <= to_slv(float_sum);
Note that the last statement doesn't convert the value; it's just an example of casting the float32 type into a std_logic_vector.