Fused AND gate in VHDL

Question

architecture Behavioral of and_44 is

variable zero_out : integer := 0;
variable temp_store : std_logic_vector(0 to 43);
variable temp_store_size : integer := 43;

variable output_count : integer := 0;

variable temp_z : std_logic := '1';

begin

for (i in 0 to 43) loop
    if (fuse_map(i) = '1') then --fuse blown
        temp_store_size := tem_store_size - 1;
        temp_store := temp_store(0 to temp_store_size); --reduce temp storage by 1
    elsif (fuse_map(i) = '0') then --fuse not blown, add to list
        temp_store((43-temp_store_size)) <= and_44(i);
    end if  ;
end loop;


for j in 0 to temp_store_size loop
        temp_z <= temp_z and temp_store(j);
end;

z <= temp_z;

end behavioral; 

im trying to create a 44 input AND gate that has fuses such that inputs can be selected based on the fuse_map. I need to know if this line is correct and allowed:

temp_store := temp_store(0 to temp_store_size); 

Also, my compiler is telling me I have several syntax errors in the first for loop.

Any feedback is appreciated, thanks.

Answer 1

Your description is a little vague but it seems like you want a multi-input AND gate with a way to control which inputs contribute to the output. It is often useful to think of these types of logic problems in hardware terms using the existing logical operators defined for std_logic_vector and related array types.

If we take a vector of inputs and logically OR them with a mask derived from fuse_map we will force unused inputs to '1' which can then be passed through an AND-reduce operation to perform the multi-way AND. VHDL-2002 added a set of reduce functions in ieee.reduce_pack. VHDL-2008 added native logic reduction as unary operators: and <vector>. For VHDL-93 you have to supply your own function. One caveat with this technique is that your AND gate will evaluate to '1' if all inputs are disabled in the fuse_map.

What you want to accomplish can be done in a single continuous assignment as follows:

output <= and_reduce(inputs or not fuse_map); -- VHDL-93 & 2002
output <= and (inputs or not fuse_map); -- VHDL-2008

The following entity gives a full example of how to do this. In real code you can just skip the entity and use the same technique directly if you don't need to implement this logic more than once.

library ieee;
use ieee.std_logic_1164.all;

entity and_map is
  port (
    -- Using unconstrained arrays here to maintain flexibility
    -- The inputs and fuse_map signals must have the same width or
    -- you will get an error upon elaboration.
    inputs   : in std_logic_vector;
    fuse_map : in std_logic_vector; -- '1' for active inputs
    output   : out std_logic
  );
end entity;

architecture rtl of and_map is
  -- Use this and_reduce function for VHDL-93 or the and_reduce
  -- from ieee.reduce_pack if you are using VHDL-2002
  -- or the built-in reduction and from VHDL-2008
  function and_reduce(inputs : std_logic_vector) return std_logic is
    variable result : std_logic := '0';
  begin
    for i in inputs'range loop
      result := result and inputs(i);
    end loop;

    return result;
  end function;
begin
  -- Continuous assignment sets unused inputs to '1'
  -- and then uses and_reduce to evaluate them all.
  output <= and_reduce(inputs or not fuse_map);
end architecture;

Style note: VHDL doesn't require parentheses around expressions in control structures.

The line temp_store := temp_store(0 to temp_store_size); is only valid when temp_store_size is 43. Think of the slice temp_store(0 to temp_store_size) as an implicit array variable that is temporarily created before the assignment. Once you decrement temp_store_size you are assigning between arrays of different sizes which isn't allowed.