How does an architecture do atomic swap?

Question

Regardless of the architecture implementing it, an atomic swap assembly instruction must take multiple clock cycles as it accesses RAM.

How do architectures generally guarantee that a thread doesn't get interrupted (by the clock or some other I/O device) while executing the instruction, between reading the memory and placing its contents in a register?

Answer 1

On the processor side an instruction wont get interrupted or re-arranged such that functionally the to and from are correct. On the memory controller side there must be an indication on the memory bus that this is an atomic access, not necessarily using that term, then the memory controller must insure that for that location there is nothing that happens between the read and write. The memory controller is free to mix in other operations so long as they dont affect the atomic operation. Instead it may be implemented on the processor side, the processor may insure that no operations happen, for that location, between the read and write, then the memory controller can be less smart.

Folks that sell processor IP like ARM and MIPS will have documentation you can download. You can also look at processors like the openrisc which I believe uses a wishbone interface and see how they implemented it (assuming they have an atomic swap instruction).