The problem is you are mixing up Signal clk [a]
with [Signal clk a]
. The former is basically unworkable in the HDL setting since its width is unbounded and could change from cycle to cycle.
What you can do instead is define fieldOut
wire-by-wire. The key insight is that given inputs
fieldIn = [x0, x1, x2, x3]
wordIn = [w0, w1, w2]
fieldOut = [y0, y1, y2, y3]
your output needs to be one of
if load: [x0, x1, x2, x3] = fieldIn
if shift: [y3, w0, w1, w2] = drop (lenght wordIn) fieldOut ++ wordIn
otherwise: [y0, y1, y2, y3] = fieldOut
So by zipping over fieldIn
and drop (length wordIn) fieldOut ++ wordIn
we can generate it bit by bit:
shiftReg_d2f :: Signal CLK Bool -> Signal CLK Bool -> [Signal CLK Bool] -> [Signal CLK Bool] -> [Signal CLK Bool]
shiftReg_d2f load shift wordIn fieldIn = fieldOut
where
fieldOut = zipWith toOutput fieldIn (drop (length wordIn) fieldOut ++ wordIn)
toOutput input shifted = r
where
r = register False $ mux load (mux shift (r, shifted), input)