In Verilog, use begin ... end
for scoping.
if ((in1==1)&&(y==0))
out1=1;
else if ((in1==0)&&(y==1))
out2 = 1;
else
out1 = 0;
out2 = 0;
end if
should be rewritten as
if ((in1==1)&&(y==0))
out1=1;
else if ((in1==0) && (y==1))
out2=1;
else
begin
out1 = 0;
out2 = 0;
end
Other if ... else ... end if
blocks should be rewritten similarly. end if
does not work in Verilog.