Which synthesis tool? It would be useful to know.
Xilinx XST 14.3 simply reports <sys_clk> is not declared.
and exits.
Add an input port for it, and it synthesises correctly, producing no hardware!
Add an output,
entity Interpretor is
Port (
SYS_CLK : in std_logic;
SCAN_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
Zero : Out Boolean
);
end Interpretor;
and a line to the architecture
Zero <= CPT_Pan = 0;
and it generates pretty much what you would expect. It still optimises away to nothing since CPT_Pan is initialised to 0, and that case is not handled at all by the process.
Dare I ask if you simulated this before trying to synthesise?