Combinational division in HDL

Question

I am trying to come up with a way to estimate the gate count if I were to implement a purely combinational 64-bit division.

I can't get my synthesis tool to generate a combinational 64-bit/64-bit integer division.

Answer 1

a 64bit/64bit divider fully combinational is leading to a huge design. this will use a lot of resources and lead to poor speed achievements. I'd suggest to implement the division with several register stages instead of fully combinational.

however, if you'd like to try, the following code would be synthesisable (as "/" operation is given by numeric_std library). check with a synthesis tool the recources needed for it (for synthesis the use of std_logic_vector in entities is suggested):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity divideComb is
Port ( a : in  STD_LOGIC_VECTOR (63 downto 0);
       b : in  STD_LOGIC_VECTOR (63 downto 0);
       c : out  STD_LOGIC_VECTOR (63 downto 0));
end divideComb;

architecture Behavioral of divideComb is

begin

    c<=std_logic_vector(signed(a)/signed(b));

end Behavioral;

the above code leads to the following synthesis results with Xilinx ISE 13.4:

• inferred 131 Adder/Subtractor(s)
• inferred 65 Comparator(s)
• inferred 4036 Multiplexer(s)

when using Spartan 6 architecture, this leads to 6982 Slice LUTs (and 0 FlipFlops, of course!)