How to check if interrupts are enabled in Cortex M3?

Question

On Cortex M3, how can a piece of code determine whether interrupts are enabled, that is, the status of the I bit in the Program Status Register (as manipulated by cpsid and cpsie)? On older ARMs, I was able to read the cpsr register, but that seems to no longer be possible.

I need this information because I have a function which is called both from main and from interrupts, and it needs to perform a certain operation atomically, while interrupts are disabled. Essentially:

bool interrupts_enabled = InterruptsEnabled();
if (interrupts_enabled) {
    __disable_irq();
}
Critical Code;
if (interrupts_enabled) {
    __enable_irq();
}

Additionally, I'd like to know how the I flag behaves when an interrupt is executed. Does execution of an interrupt ever set the I flag, as in to prevent nesting? Is interrupt nesting enabled by default, and how can I prevent nesting?

Answer 1

The exception architecture is a bit different for the M3. Interrupts are controlled using the PRIMASK, FAULTMASK and BASEPRI registers. These are accessible using the MRS and MSR instructions and are not part of the CPSR as you might find on older ARM architectures. In the simplest scenario, interrupts are masked by writing 1 to the PRIMASK and unmasked by writing 0 to PRIMASK. PRIMASK can be read to determine its state. If you need control over the NMI or hard fault, then FAULTMASK comes into play. If you want finer control using priorities, then BASEPRI is used. You will have to do a bit of reading to determine what your usage needs to be and the role of priorities in whether or not nested interrupt execution is allowed.