What are fast LEA and slow LEA unit in the microarchitecture of Inte's CPU?

Question

I saw haswell's microarchitecture from below link mentioned that some pipelines can carry on fast LEA and some can run slow LEA, what's the meaning of fast LEA and slow LEA here? Related to LEA instruction? The search results are usually biases to LEA instruction, and don't lead to direct answer.

http://www.realworldtech.com/haswell-cpu/4/

Answer 1

Most dedicated ALU units exist only on part of the execution ports (with constant changes being made from generation to generation), the CPU has to pick one of the possible ports according to the instruction (or rather the micro-operation) being performed. When Multiple identical ports can do the same, it should attempt to do some balancing, and there may be other possible factors. The exact algorithm of course is never published.

In this case however, the LEA operations are split into slow and fast ones, according to this link, the slow ones are due to using 3 operand LEAs (base, index, offset). It actually also provides you with a performance monitor to measure how many such cases you encounter.