I'm not sure your question is entirely clear, but I think you're asking how much data can be transferred to or from L1 cache upon execution of a single x86 instruction?
If so, it's kind of an ill posed question. The cache structure, and even caching as a concept are not part of the x86 specification. This means, that the answer depends entirely on the underlying hardware. If there's a specific processor you have in mind, you can probably find the answer in the data sheet. What you're looking for is the cache block size, since cache managers like to write and read whole blocks at a time. However, there are instructions in x86 extensions (such as AVX and SSE) that deal specifically with large memory transactions, and they can write or read the cache as much as is required/convenient.