How does undefined input affect the selection?

Question

I am writing a verilog file. I am using the following code to function as a multiplexer:

assign out = raddr_mux ? a:b

However, the output wave seems strange.

As you can see at the lower part of the image, the red line indicates that the raddr_mux is not defined. However, sometimes, the output out got value, sometimes the output out has nothing. I am wondering how the undefined will affect the selection behavior. Thank you!

Answer 1

An x on an input means undefined, that is it is either 0 or 1.

If both inputs to a mux are at the same value it does not matter what the select value is, the output is still defined as it has to be one of the inputs. In our example the select is x but both inputs and output are 0, 4 then 5.

If the inputs are not the same, the output is x, it is undefined as it could be either of the input values.