Detecting three consecutive set bits in Verilog

Question

I have an error with my code . I've got a given 32b input and an 6b output which should be incremented everytime when the input has 3b of 1 consecutively . For example if the input is 000...111 the output should be 000001.

I tried this code :

input [31:0] in,
output reg [5:0] out,
input clock

assign n=0;
always @ (posedge clock) begin
**out <= in[n]?in[n+1]?in[n+2]? out+1 : out;**
n++;
end

with no success . Any ideas ?

Answer 1

This can be solved using the elegant solution posted here:

if  (in & (in >>1) & (in>>2)  != '0 )
 out <= out+1;

Basically, if the the bitwise AND of the number with itself shifted 1 bit to the right for three times is non-zero, you increment.