endmodule error while compiling

Question

I am trying to code a memory test algorithm in Verilog. This code is a part of it. I am trying to write a state machine to set the read select signal. I am getting compilation errors like :

near "endcase": syntax error, unexpected endcase.

Any help would be appreciated.

This is my code:

module testarch (q, clk, reset, data_in, r_s);

input clk;
input reset;
output [0:2] q;
output data_in;
output r_s;

reg data_in; 
reg [0:2] q;    // address location
reg [0:2] state;       // state machine
reg r_s;
integer done=0;
reg [0:1] l=0;

 always@(posedge clk or posedge reset or state)
    begin //1
    if(reset)
        begin
        state <= 1;
        q<=0;
        end
     else
        begin
        case(state)
        1 : //first four stages
            begin
            repeat (8)
                begin
                @(posedge clk)
                    begin
                    while (!done)
                    begin
                    case(l)
                        0: 
                        begin
                        q<=q;
                        end
                        1: 
                        begin
                        q<=q;
                        end
                        2: 
                        begin
                        q<=q;
                        end
                        3: 
                        begin
                        q<=q+1;
                        done<=1;
                        end
                        endcase
                    end
                    end

                 @(negedge clk)
                    begin
                    while (!done)
                    begin
                    case(l)
                        0: 
                        begin
                        l<=l+1;
                        r_s<=1;
                        end
                        1: 
                        begin
                        l<=l+1;
                        r_s<=1;
                        data_in<=1;
                        end
                        2:
                        begin
                        l<=l+1;
                        r_s<=1;
                        data_in<=0;
                        end
                        3: 
                        begin
                        l<=l+1;
                        r_s<=1;
                        data_in<=0;
                        end
                        endcase
                    end
                    end
                end // end repeat
            endcase
         end //end else
     //end //end always
 endmodule 

Answer 1

You have a missing "end" between the end that is labelled with the comment "end repeat" and the "endcase" (because there's a "begin" before the repeat that needs to be closed before you can close the case).

This isn't entirely obvious because the indentation style you're using is confusing. I reindented the code so I could see what is going on, and I suggest using a style closer to this one in future because it does make it easier to find problems like this:

module testarch (q, clk, reset, data_in, r_s);

input clk;
input reset;
output [0:2] q;
output data_in;
output r_s;

reg data_in; 
reg [0:2] q;    // address location
reg [0:2] state;       // state machine
reg r_s;
integer done=0;
reg [0:1] l=0;

 always@(posedge clk or posedge reset or state)
 begin //1
    if(reset)
    begin
        state <= 1;
        q<=0;
    end
    else
    begin
        case(state)
         1 : //first four stages
             begin
                repeat (8)
                begin
                    @(posedge clk)
                    begin
                        while (!done)
                        begin
                           case(l)
                            0: 
                               begin
                                   q<=q;
                               end
                            1: 
                               begin
                                   q<=q;
                               end
                            2: 
                               begin
                                   q<=q;
                               end
                            3: 
                               begin
                                   q<=q+1;
                                   done<=1;
                               end 
                           endcase
                        end
                    end

                    @(negedge clk)
                    begin
                        while (!done)
                        begin
                            case(l)
                             0: 
                                begin
                                    l<=l+1;
                                    r_s<=1;
                                end
                             1: 
                                begin
                                    l<=l+1;
                                    r_s<=1;
                                    data_in<=1;
                                end
                             2:
                                begin
                                    l<=l+1;
                                    r_s<=1;
                                    data_in<=0;
                                end
                             3: 
                                begin
                                    l<=l+1;
                                    r_s<=1;
                                    data_in<=0;
                                end
                            endcase
                        end
                    end
                 end // end repeat
               // MISSING "end" SHOULD BE HERE!
            endcase
         end //end else
     //end //end always
 endmodule