How to use user defined types in a vhdl submbodule?

Question

Lets say I have the following in my top level .vhd file

entity toplevel is
....
end toplevel;
architecture behave of toplevel is
type state is (A, B, C);
signal cur_state : state;
...
E1 : entity submodule_entity port map(
...
cur_state => cur_state);
...
end behave;

and in the entity/architecture pair of my second file I have the following

entity submodule_entity is
port(
    ...
    cur_state : in state);
end entity;

The synthesizer complains that the type state is not defined in submodule_entity (which makes sense). How would I go about using a user defined type in another module?

Answer 1

You need to put the custom type(s) in a package that you then include in both entities.