Divide a clock by 3 without changing the duty cycle?

Question

I searched a lot but I didn't find a good solution. Most answers work only when the duty cycle is 50% but I am searching for a solution that works for clocks with duty cycles like 40%, etc.

Answer 1

SYNCHRONOUS

You will find it hard to do this with a synchronous design because the flip-flops can only switch on a clock edge.

Typical divide by 3 circuits will either:

1. Use positive clock edges and have a 33% output duty cycle

2. Use positive and negative edges and have a 50% duty cycle if the input is 50%

Unfortunately, for a general input duty cycle such as 40%, if you sketch out the location of the clock edges you will find they occur at:

0,0.4,1,1.4,2,2.4,3

but for a 40% divide by 3 you would require edges at separated by 1.2 (=0.4*3) and 1.8, but such differences are not available to you. (You only have differences such as 0.4,0.6,1.0,1.4,1.6,etc.)

ASYNCHRONOUS

The standard way to get a divide by 3 with a different duty cycle is simply to instantiate a delay locked loop or a phase locked loop circuit.

For example, if you are using an Altera FPGA look at the AltPLL megafunction which has options to set the target duty cycle, and will work across a wide range of input duty cycles.

However, note that the output duty cycle is set when you configure the PLL and will not track the input duty cycle.