Reuse the same function in 2 Verilog modules

Question

I have a function f(), defined in a Verilog module, M1. I would like to reuse this same function in a different module, M2.

Is there anyway of doing this without redefining the function in M2?

  --- M1.v ---
  module M1();
     function f;
        //do stuff
     endfunction
  endmodule

  --- M2.v -----
  module M2();
  // Use f() here
  endmodule

Answer 1

You can place the function into a separate file and use the `include compiler directive to include the function inside both modules:

  --- M1.v ---
  module M1();
     `include "functions.v"
  endmodule

  --- M2.v -----
  module M2();
     `include "functions.v"
     // Use f() here
  endmodule