Intermediate representation for FPGA compilers

Question

When writing compilers for standard computers, one can target an existing intermediate representation (like LLVM IR) and not have to worry about tricky architectural differences between systems. Does something like this exist for FPGAs?

Answer 1

Not really. The synthesis tools are very architecture-aware already, so the output netlist is already tailored to the target device.

The closest you could come would be to use ASIC tools to target a simple library of gates and flipflop. That would produce a "lowest-common denominator" netlist (although it wouldn't then be efficient to re-target to an FPGA as getting back from that representation to "it was an adder, so I can use the carry-chain" is non-trivial.

Update - I see you want to develop an experimental HDL...

I would suggest that if you want to go from your experimental HDL to a bitstream that you just output VHDL or Verilog and then run the traditional tools. My feeling is that you really don't want to be responsible for mapping (eg) adders to LUTs+carry chains, as it'll take you years to be as good as the current tools.

If you haven't already, take a look at how MyHDL does a similar thing.