Using a shell variable within Makefile

Question

I have a line line in make file for compiling a c program, which goes like this $(CC) -c -o $@ $< $(CFLAGS). I have to modify a particular line in code every time and compile again. Modification is just an argument to a function. I have the argument in one file and i use sed utility to modify my c source and then compile. I want to see which of the arguements leads to successful compilation. I tried to use this $(CC) -c -o $@ $< $(CFLAGS) ; echo $? >status where I was hoping if compilation was successful status file would have an entry 0. But i see the source file name in status file. I came to know that $? is also a make automatic variable. How can i read the shell variable $? within makefile ? I have tried using $(CC) -c -o $@ $< $(CFLAGS) ; echo $$? >status and $(CC) -c -o $@ $< $(CFLAGS) ; echo $(shell echo $?) >status without getting correct results.

Answer 1

The version

echo $$? > status

definitely works for me. What OS are you using? What are the incorrect results when using $$??

If you are on Windows, there is no $?, you might want ot use %errorlevel% instead.