Problems with simulation in Active-HDL

Question

I generated Xilinx aurora8b10b lane core. Together with the core there are work example and macros for simulation (simulate_mti.do). When i execute macros core is compiled but in Waveform Viewer signals don't appears (error: # No signals matching).

I manually compile core and execute this macro:

set XILINX   $env(XILINX)

# Create and map a work directory 
vlib work
vmap work work
vsim -L secureip -L unisims_ver -t ps aurora_example.EXAMPLE_TB aurora_example.glbl -     voptargs="+acc" -GUSE_CHIPSCOPE=0
view wave

#do mti_wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0



add wave -noupdate -divider {aurora_8b10b_v5_2 Core 1}
add wave -noupdate -divider {Core 1 LocalLink TX Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_D
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_REM
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_SRC_RDY_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_SOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_EOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_DST_RDY_N
add wave -noupdate -divider {Core 1 LocalLink RX Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_1_i/aurora_module_i/RX_D
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/RX_REM
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/RX_SRC_RDY_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/RX_SOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/RX_EOF_N
add wave -noupdate -divider {Core 1 Error Detection Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/HARD_ERR
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/SOFT_ERR
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/FRAME_ERR
add wave -noupdate -divider {Core 1 Status Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/CHANNEL_UP
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/LANE_UP
add wave -noupdate -divider {Core 1 Clock Compensation Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/WARN_CC
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/DO_CC
add wave -noupdate -divider {Core 1 System Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/clock_module_i/PLL_NOT_LOCKED
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/RESET
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/POWER_DOWN
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_OUT_CLK
add wave -noupdate -divider {Frame Checker Error Count for Core 1 }
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_1_i/ERR_COUNT



add wave -noupdate -divider {aurora_8b10b_v5_2 Core 2}
add wave -noupdate -divider {Core 2 LocalLink TX Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_D
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_REM
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_SRC_RDY_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_SOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_EOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_DST_RDY_N
add wave -noupdate -divider {Core 2 LocalLink RX Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_2_i/aurora_module_i/RX_D
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/RX_REM
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/RX_SRC_RDY_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/RX_SOF_N
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/RX_EOF_N
add wave -noupdate -divider {Core 2 Error Detection Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/HARD_ERR
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/SOFT_ERR
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/FRAME_ERR
add wave -noupdate -divider {Core 2 Status Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/CHANNEL_UP
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/LANE_UP
add wave -noupdate -divider {Core 2 Clock Compensation Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/WARN_CC
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/DO_CC
add wave -noupdate -divider {Core 2 System Interface}
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/USER_CLK
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/clock_module_i/PLL_NOT_LOCKED
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/RESET
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/POWER_DOWN
add wave -noupdate -format Logic /EXAMPLE_TB/example_design_2_i/aurora_module_i/TX_OUT_CLK
add wave -noupdate -divider {Frame Checker Error Count for Core 2 }
add wave -noupdate -format Literal /EXAMPLE_TB/example_design_2_i/ERR_COUNT




TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {26705705 ps}
configure wave -namecolwidth 273
configure wave -valuecolwidth 37
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
run -all

Log:

wave -noupdate -format Logic /EXAMPLE_TB/example_design_1_i/aurora_module_i/USER_CLK
# No signals matching
wave -noupdate -format Literal /EXAMPLE_TB/example_design_1_i/aurora_module_i/TX_D
# No signals matching

etc

I used verilog, Active-HDL 9.1 Expert (mixed languages), ISE 13.2 COREgen, Xilinx Virtex-5, Standart Waveform Viewer.

I connected the following libraries: unisims_ver, unisim, unimacro, VIRTEX5, xilinxcorelib, xilinxcorelib_ver, secureip

Verilog optimization disable. Generate data to Advanced Dataflow enable. Acces to design objects - all enable except "Limit read acces to design top-level signals only"

I read lot of information on Xilinx.com, but didn't find the answer.

Answer 1

I found an excellent solution for this problem - using of the ISE WebPack and ISim.I created new project, connected a core, testbench, began simulation and everything works (without a lot of settings in Active-HDL).