Either method will work. The best result is dependent on the how smart/dump your synthesizing tool is. Some tools issue warnings when it sees an overflow is possible. If you want to resolve the warning, you can use the below method:
reg [7:0] count = 0;
wire [8:0] next_count = count + 1'b1; // MSB is overflow bit
always @(posedge Clk)
count <= next_count[7:0]; // overflow bit not used in assignment
The overflow bit could be done in the synchronous block. Unless you plan on using the overflow bit, I would not recommend these as it will either waste a flop (dumb synthesizer) or issue a warning that a flop has been optimized out (smart synthesizer).
reg [7:0] count = 0;
reg overflow;
always @(posedge Clk)
{overflow,count} <= count + 1'b1; // optimization warning OR wasted flop