Digital Logic - realizing full adder using NAND gates?

Question

I am stuck while solving this question,

What is the minimum number of 2 input nand gates required to realize

I found the answer when there is no limit on the number of inputs, but cant find the answer when the constraint "2 input nand gate" is specified". Any help would be appreciated.

Answer 1

Well, what you tried? (Since it sounds like homework ;-)

I suggesting reading Wikipedia: Adder. It gives the schematics for a full-adder using a combination of AND/OR/XOR gates. Note that these gates can be made from just (2-input) NAND gates ... then it's just a matter of minimizing.

Happy learning.