Verilog Error: Can't elaborate user hierarchy “counter:counter”

Question

I'm tring to write snake from LED on a Quartus Board. It's kind of like KITT-Leds, but when I try to run my program, I get an error.

module ukol3(KEY,LEDR);
input[1:0]KEY;
output[14:0] LEDR;

counter counter(KEY[0], KEY[1], LEDR[14:0]);

endmodule

module counter(C,CLR,Q);
input C, CLR;
output [14:0] Q;
reg [14:0] tmp;
integer i;

always @(posedge C or posedge CLR)      
    begin

        if (CLR)
            tmp = 15'b000000000000000;

        if (tmp == 15'b111111111111111)
            i = 0;

        if (tmp == 15'b000000000000000)
            i = 1;

        if (i == 1)
            tmp = tmp + 1'b1;

        if (i == 0)
            tmp = tmp - 1'b1;
        end 
    assign Q = tmp;


endmodule

This gives me an error:

Error: Can't elaborate user hierarchy "counter:counter"

I really don't know what's going on.

Answer 1

This question is about Verilog, not vhdl. I want to ask a couple of questions: Is your code synthesizable? and what do you get after a synthesis module counter?

For your question, I think you should compile counter first, then compile ukol3. The EDA tool will not find counter when you didn't did it first. You should split it into two separable files and do the counter first.

P.S.: You should use a better mapping port method such as counter counter (.C(KEY[0]),.CLR (KEY[1]),.Q (LEDR[14:0])); for clearer code.