Yes, it is 'stuck' as you would say. Only one 'loop' of the block can be active at a time, it will not reenter if it has not completed the loop.
The thing you are trying to do there is likely not synthesizable, due to the wait operations inside the block.
I don't know the exact specifics of your design, but I would approach this with a small finite state machine. I assume that the signals from your subsystem are not faster than the clock, so it would look something like:
always @* begin
if(state_f == `WAIT_FOR_FIRST)
state_nxt = got_first_signal ? `WAIT_FOR_SECOND : `WAIT_FOR_FIRST;
else if(state_f == `WAIT_FOR_SECOND)
state_nxt = got_second_signal ? `DONE_STATE : `WAIT_FOR_SECOND;
else if(state_f == `DONE_STATE)
state_nxt = `WAIT_FOR_FIRST;
else
state_nxt = 2'bxx;
end
always @(posedge clk) begin
state_f <= state_nxt;
end