alignment requirement for powerpc icbi and dcbf cache instructions

Question

I have inherited some PowerPC 750FX code. A handful of functions flush the instruction and data cache with

icbi  0,3   # instruction cache block invalidate

and

dcbf  0,3   # data cache block flush

respectively. The code makes sure the Register 3 contents is 32 byte aligned so it always points to the start of a cache line. I wonder if this is necessary. The PowerPC manual only talks about computing the effective address (EA) using the operands, but has nothing to say about alignment requirements of the resulting EA. Is it safe to execute these instructions with arbitrary EA addressing any byte within a cache line?

Answer 1

That would deserve a test but from what I've read (what is the same in various cores reference manuals and PowerISA 2.05), there is no need to align data address. The action points on the block that contains the address.

If the block containing the byte addressed by EA is in storage that is Memory Coherence Required and a block containing the byte addressed by EA is in the instruction cache of any processors, the block is invalidated in those instruction caches, so that subsequent references cause the block to be fetched from main storage.

I don't know your code but is the alignment is done at the beginning and then a loop adds the cache block size to the EA?