If it is the walking 0's pattern that your after how about:
localparam SHIFT_W = 3;
localparam OUT_W = 2**SHIFT_W;
reg [SHIFT_W-1:0] shift;
reg [OUT_W-1:0] out;
always_comb begin
out = ~(OUT_W'(1'b1 << shift));
end
As suggested by nguthrie. Shift to create a walking 1, then invert to create a walking 0.
My original suggestion (which was a bit verbose) using SystemVerilog to directly create a walking 0:
localparam SHIFT_W = 3;
localparam OUT_W = 2**SHIFT_W;
reg [SHIFT_W-1:0] shift;
reg [OUT_W-1:0] out;
always_comb begin
out = OUT_W'( $signed{ 1'b1, 1'b0, {OUT_W{1'b1}} }) >>> (OUT_W-shift) );
end
WIDTH`()
Casts to the correct width to stop LHS RHS width mismatch warnings.
$signed()
Casts to a signed number to allow >>>
to shift by sign extending. This could also be written as:
out = OUT_W'( { {OUT_W{1'b1}}, 1'b0, {OUT_W{1'b1}} } >> (OUT_W-shift) );
For Verilog-2001, you will just get LHS RHS width mismatch warnings:
out = { {OUT_W{1'b1}}, 1'b0, {OUT_W{1'b1}} } >> (OUT_W-shift);
Which has removed the need to sign extend during shift.